Energy-efficient hardware/software co-synthesis for a class of applications on reconfigurable SoCs

Reconfigurable System-on-Chip (RSoC) devices incorporate various components, such as processor core, reconfigurable logic, memory, etc., onto a single chip. They are being used to implement many wireless embedded systems, where energy efficiency is a major concern. When an application is synthesized on RSoCs, part of it can be executed using hardware implementations on the reconfigurable logic or software implementations on the processor core. Besides, the communication and reconfiguration costs between the tasks can significantly impact the overall system energy dissipation depending on how the application is synthesized on RSoC. In order to develop applications on RSoCs for energy efficiency, we propose a threestep design process in this paper. We develop (a) a performance model to abstract a general class of RSoC architectures for application development, (b) a mathematical formulation of the energy-efficient synthesis problem for a class of applications, and (c) a dynamic programming algorithm that minimizes the system energy dissipation. We illustrate our approach by implementing two beamforming applications on a state-of-theart RSoC device. Beamforming is one of the key techniques for improving the capacity of wireless systems such as software defined radio. Compared with a greedy algorithm, reduction in energy dissipation ranging from 41% to 54% is observed in our experiments.